Without limiting the scope of the invention, its background is described in connection with a synchronous circuit coupled to an asynchronous bus interface, such as an integrated circuit or circuit board coupled to an asynchronous system bus.
In systems using an asynchronous bus to couple devices, or in coupling two devices each clocked on unrelated clock time domains, the receiving device contains synchronous circuitry which must be able to reliably receive data from the asynchronous bus and capture data from it without missing the next data word to be sent on the bus. To accomplish this the asynchronous signals present at the bus interface must be synchronized to the time domain used within the synchronous receiving circuit.
Heretofore, in the design of asynchronous bus coupling circuitry, the typical approach to these problems was to provide a multiple ported FIFO buffer which couples the two time domains by capturing data from the bus, disabling further writes by the bus, and then allowing the synchronous circuitry to read the data out, which in turn enables subsequent writes by the bus logic. While effective in providing reliable operation, the FIFO approach of the prior art is gate count intensive and complex. Alternatively, the receiving device may handshake with the sending device through a system of data flags and wait signals which prevent the asynchronous data from changing or disappearing while the receiving device is reading it, essentially holding off subsequent data words. This approach has the disadvantage of tying up the bus, and thus slowing down the data rate, as well as requiring additional signal channels on the bus interface. In order for this prior art approach to work, it is required that the asynchronous event or signal being detected remain present until the synchronous receiving circuit acknowledges that it has successfully captured the data, a requirement which results in the bus being unavailable for extended time periods.
A need for an efficient method and apparatus for synchronizing asynchronous data signals, without requiring additional handshaking signals or unduly restricting the duration of such signals or events on an asynchronous bus, thus exists. Accordingly, improvements which overcome any or all of the above discussed problems are presently desirable.